The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
ICs may include a plurality of standard cell circuits each formed by various logic components, such as transistors, capacitors, or the like, to provide a Boolean logic function or a storage function. Interconnect structures, such as vias and power rails, are then formed over the plurality of standard cell circuits to provide connections between the standard cell circuits and/or to provide connections to external devices. However, as the size of standard cells progressively become smaller, gaps and clearance between the power rails and the other electronic components may decrease which may increase the risk of shorting. Attempts to reduce the size of the power rails, however, may suffer from increased resistance and may induce speed degradation. Accordingly, what is needed is a circuit structure and a method of making the same to address the above issues.